1. Field of the Invention
The present invention relates to solid-state imaging devices and, more specifically, to a solid-state imaging device in which a pixel includes a conversion section that converts an electric charge generated by photoelectric conversion into a pixel signal, e.g., CMOS (Complementary Metal Oxide Semiconductor) sensor. The CMOS sensor is manufactured through entire or partial application of a CMOS process.
The solid-state imaging device may be a one-chip element, or configured by a plurality of chips.
2. Description of the Related Art
For MOS (Metal Oxide Semiconductor) devices, LOCOS (Local Oxidation of Silicon) isolation has been generally used for element isolation. In recent years, to deal with smaller device size, STI (Shallow Trench Isolation) is getting popular for element isolation.
In solid-state imaging devices such as CMOS sensors, STI is also getting popular for element isolation (refer to Patent Document 1 (JP-A-2002-270808)). A solid-state imaging device is configured by a pixel area, and a peripheral circuit that drives the pixel area for signal processing. The size reduction technology for the peripheral circuit is adopted also for the pixel area. For pixels in any recently-size-reduced solid-state imaging device, STI is also generally used for element isolation similarly to the peripheral circuit.
FIG. 24 shows the cross sectional configuration of the main section of a previous solid-state imaging device to which STI is applied. In this STI-applied solid-state imaging device 1, an n-type silicon substrate 2 is formed with a p-type semiconductor well area 3. The p-type semiconductor well area 3 is formed with a trench 4, and inside of the trench 4, a silicon oxide film 5 is embedded so that an STI area 6 is formed. This STI area 6 is an element isolation area that applies element isolation inside of a pixel and between any two adjacent pixels. With the STI area 6, two adjacent pixels 10A and 10B are isolated from each other, and in the pixels 10A and 10B, photodiodes PD or a plurality of transistors are also isolated from one another, for example. Note here that a pixel is configured by a photodiode PD serving as a photoelectric conversion section, and a plurality of transistors Tr.
The photodiode PD is of an HAD (Hall Accumulated Diode), configuration including the so-called n-type substrate 2, the p-type semiconductor well area 3, an n-type charge storage area 7, an insulation film 8 on the surface side, and a p+ accumulation layer 9. Out of a plurality of transistors, a transfer transistor is specifically configured by forming a transfer gate electrode 13. In the transfer gate electrode 13, a gate insulation film 12 is disposed between the n-type charge storage area 7 of the photodiode PD, and an n-type drain area 11 serving as a floating diffusion (FD). To the STI area 6, a p+ area 14 is formed at an interface among the deeply-embedded silicon oxide film 5, the n-type charge storage area 7, and the p-type semiconductor well area 3. The p+ area 14 is provided with the aim of preventing dark currents and white spots.
With the solid-state imaging device using the above-described STI as a technology of pixel area isolation, however, two problems are observed as below. The first problem is that a crystal defect easily occurs due to thermal stress. With the STI, the trench 4 is formed with a depth to the silicon substrate, and the silicon oxide film 5 is embedded therein so that the element isolation area 6 is formed. With such a configuration, there is indeed an advantage of forming a small-sized element isolation are, however, a difference of thermal expansion coefficient between the deeply-embedded silicon oxide film 5 and the silicon substrate causes the thermal stress. For improvement, some design change is made like the shape for STI is tapered, for example. With the tapered shape, however, the area of the photodiode PD is reduced, resulting in the fewer amount of saturation signal, and the poorer sensitivity.
The second problem is the p+ area 14 disposed between the silicon oxide film 5 in the trench 4 and the photodiode PD for the aim of preventing the dark currents and white spots. This P+ area 14 is required to have the impurity concentration of a level about the same as that of the p+ accumulation layer 9 on the surface of the diode PD. However, in terms of configuration, covering three-dimensionally the depth direction with sufficient concentration is difficult. What is more, because the p+ area 14 is formed in the initial stage, the p+ area 14 is expanded to the side of the photodiode PD due to the thermal diffusion. This resultantly reduces the area of the photodiode PD, thereby causing the reduction of the amount of saturation signal.